The present invention relates generally to memory devices and in particular the present invention relates to integrated circuit memory devices having multiple data communication connections.
Packaged integrated circuit memory devices typically include a semiconductor die or chip which is encapsulated in plastic. The integrated circuit chip is connected to a printed circuit board through electrical conductors called leads. During manufacturing, all leads are typically connected together in what is referred to as a lead frame. The lead frame is electrically attached to the die using thin wire, typically made of gold, which is bonded to both the lead frame and bond pads provided on the chip surface. The chip and a portion of the lead frame is then encapsulated in plastic and the interconnections of the various conductors of the lead frame are removed to leave independent, electrically isolated leads.
It is known to those skilled in the art that multiple bond pads or multiple bond wires can be used to attach power and ground leads to an integrated circuit. These arrangements can be used to simplify power distribution throughout the integrated circuit. In contrast, only one bond pad is provided for each data lead of the memory device. Thus, multiple lengthy conductors are provided on the die if several circuits located remotely on the die must be connected to a common lead. These conductors reduce the operating efficiency of the memory and require available real estate. Further, data communication connections (DQ""s) use a single input/output buffer circuit in conjunction with each bond pad to which the multiple conductors are connected. The single buffer and the long conductors in combination increase the complexity of the die and reduce the operating time efficiency of the memory device.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device which eliminates the need for data communication paths on an integrated circuit die from multiple remote circuits to a common data buffer and bond pad.
The above-mentioned problems with integrated circuit memories and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A memory device is described which uses distributed input/output buffers and multiple bond pads for data communication connections.
In particular, the present invention describes an integrated circuit memory device comprising an integrated memory die having multiple bond attachment pads, and a conductive leads connected to the bond attachment pads such that some of the conductive leads are connected to more than one bond attachment pad.
In another embodiment a memory device is described which comprises a plurality of conductive leads, and an integrated circuit memory chip. The memory chip comprises an array of memory cells arranged in subarrays, bond pads fabricated on the integrated circuit memory chip and electrically coupled to the subarrays, the bond pads are electrically connected to the conductive leads such that the bond pads are connected to one of the conductive leads.
A method of reducing data communication time in an integrated memory circuit is described. The method comprises the steps of fabricating an integrated memory circuit on a semiconductor die having bi-directional data communication circuits coupled to a plurality bond pads distributed over the die, providing a lead frame having an electrically conductive lead for bonding to the distributed bond pads, and bonding the bond pads to the electrically conductive lead for bi-directional data communication with an external processor.
In yet another embodiment, a bi-directional data communication system is described. The system comprises a processing unit, and a memory device connected to the processing unit through data communication connections. The data communication connections comprise electrically conductive leads. The memory device is fabricated as a semiconductor die and comprises an array of memory cells arranged in a plurality of subarrays, a plurality of bond pads fabricated on the integrated circuit memory chip and electrically coupled to the plurality of subarrays. The plurality of bond pads are electrically connected to the plurality of conductive leads such that a plurality of bond pads are connected to each one of the plurality of conductive leads.